The present invention relates to a stacked complementary metal oxide semiconductor inverter (referred to as a stacked CMOS inverter).
A stacked CMOS inverter with a cross section shown in FIG. 1 has been known. In FIG. 1, a field oxide layer 2 for electrically isolating semiconductor elements one from another is provided on one of the surface regions of a P type silicon substrate 1. An n.sup.+ type source region 3 and an n.sup.+ type drain region 4, which are electrically isolated from each other, are provided in the land substrate region isolated by the field oxide layer 2. A gate oxide layer 5 is provided on the surface of the substrate region located between the source and drain regions. A gate electrode 6 is laid over the gate oxide layer 5. The surfaces of the gate electrode 6, the source region 3 and the drain region 4 are covered with a CVD-SiO.sub.2 layer 7. The SiO.sub.2 layer 7 on the surface of the gate electrode 6 serves as a gate oxide layer of a p-channel MOS transistor to be described later. A through-hole 8 is formed in a part of a region of the CVD-SiO.sub.2 layer 7, which faces the source region 3. A polycrystalline silicon layer 9 is provided laying over the gate electrode 6, at least a portion of the source region 3, and the drain region 4. A portion of the polycrystalline silicon layer 9, which is located facing the gate electrode 6, is formed as an electrical isolating layer. A portion of the same, which faces the source region 3, is used as a p.sup.30 source region 10. A portion of the same confronts a p.sup.30 drain region 11. The p.sup.30 source region 10 is in contact with the n.sup.+ source region 3 through the through-hole 8 of the CVD-SiO.sub.2 layer 7. The entire surface of the semiconductor device of FIG. 1 containing the polycrystalline silicon layer 9 is covered with an interlayer insulation layer 12 made of CVD-SiO.sub.2 layer. An aluminium interconnection electrode 14 (power source electrode), which comes in contact with the n.sup.+ drain region 4 through a contact hole 13 passing through the interlayer 12 and the CVD-SiO.sub.2 layer 7, is formed on the insulation layer 12. Also formed on the insulation layer 12 is another aluminium interconnection electrode 15 (the other power source electrode) connected to the p.sup.30 drain region 11 through the contact hole 13 passing through the insulation layer 12. Another aluminium connection electrode 16 (signal output electrode) is further formed on the insulation layer 12 and is connected to the p.sup.30 source region 10 through a contact hole 13 passing through the insulation layer 12. The CMOS inverter thus structured contains an n-channel MOS transistor formed in the semiconductor substrate 1, a p-channel MOS transistor formed by the polycrystalline silicon layer 9 layered through an insulation layer over the n-channel MOS transistor, the gate electrode 6 being commonly used for the n-channel MOS transistor and the p-channel MOS transistor.
An equivalent circuit of the CMOS inverter shown in FIG. 1 is illustrated in FIG. 2. In the circuit, Q1 corresponds to the p-channel MOS transistor, Q2 the n-channel MOS transistor, and G the gate electrode 6, O a signal output electrode 16, V.sub.DD a power source electrode 15, and V.sub.SS a power source electrode 14. Normally, the power source electrode V.sub.SS is set at an earth potential and the power source electrode V.sub.DD at 1 to 5 V, for driving the inverter.
In the inverter shown in FIG. 1, the signal output electrode 16 normally contacts the p.sup.30 source region 10 of the polycrystalline silicon layer 9 forming the p-channel MOS transistor. The source region 3 of the n-channel MOS transistor directly contacts the source region 10 of the p-channel MOS transistor through the through-hole 8. Therefore, a p-n junction is formed between the source regions 3 and 10. Accordingly, as shown in FIG. 2, a parasitic diode D1 with a polarity as shown is formed between the source region 3 of the n-channel MOS transistor Q2 and the signal output terminal O. When the parasitic diode D1 is present, the output signal voltage from the output signal terminal O exhibits a response characteristic against an input signal voltage supplied to the gate terminal G, as shown in FIG. 3. To be more specific, with an increase of the amplitude of the input signal voltage applied to the gate terminal G, when the p-channel MOS transistor Q1 is in an OFF state and the n-channel MOS transistor Q2 is in an ON state, the output voltage from the signal output terminal O cannot have the level of V.sub.SS, but has a level of V.sub.B which is a potential difference at the p-n junction of the parasitic diode D1. In other words, the amplitude of the output signal voltage becomes smaller by V.sub.B than when the parasitic diode D1 is not present. This implies that it is very difficult to distinctively recognize the level state of the output signal voltage, that is, whether the level of the output signal voltage is "0" or "1". Normally, the potential difference at the p-n junction is approximately 0.7 V. Accordingly, when the power source voltage V.sub.DD is low, it is very difficult to distinguish the different level states of the output signal voltage.
The CMOS inverter, in which a p-channel MOS transistor is formed in the silicon substrate 1 and an n-channel MOS transistor is formed by the polycrystalline silicon layer 9, is also attendent with the parasitic diode. In this case, as shown in the equivalent circuit of FIG. 4, the p-channel MOS transistor is denoted as Q1' and the n-channel MOS transistor as Q2'. The parasitic diode D2 is inserted between the signal voltage output terminal O and the source of the transistor Q1'. A graph in FIG. 5 represents a response characteristic of an output signal voltage against an input signal voltage level to the gate G. In this case, the power source voltage V.sub.DD is reduced by a potential difference V.sub.B at the p-n junction of the parasitic diode D2, and is derived from the output signal terminal O.